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ホーム > Other > Design of high-speed data acquisition card based on EP2C8Q208 and TMS3

Design of high-speed data acquisition card based on EP2C8Q208 and TMS320VC5416 chip

公開時間: 2020-05-19 16:00:34

Introduction

At present, many fields increasingly require high-precision A / D conversion and real-time processing functions. At the same time, the market's requirements for supporting more complex display and communication interfaces are also increasing, such as environmental monitoring, electricity meters, medical equipment, portable data acquisition, and industrial sensors and industrial control. The traditional design method is to use the MCU or DSP to control the A / D conversion of data acquisition through software. This will frequently interrupt the operation of the system, thereby weakening the system's data calculation capability and the speed of data acquisition will also be limited. This article uses the DSP + FPGA scheme, the hardware controls the A / D conversion and the data storage, maximizes the system signal acquisition and the processing ability.

system structure

The entire acquisition card includes signal conditioning, data acquisition, data processing, and bus interface design. The system structure is shown in Figure 1.

Figure 1 System structure block diagram

This paper designs a signal conditioning circuit with functions such as signal attenuation, gain amplification, and filtering. It uses the AD7676 A / D converter with 16-bit precision and a maximum sampling rate of 500KSPS. The digital system design uses the extremely flexible and programmable characteristics of FPGA. Altera's FPGA chip EP2C8Q208 completes accuracy correction and logic timing control; DSP uses TI's TMS320VC5416 to make the data after A / D conversion be sorted, marked, packaged, and preprocessed before being transmitted to the host computer. The data acquisition card can perform 8-channel data acquisition at the same time, and the channel can be set for attenuation factor, sampling speed and amplification gain. At the same time, it provides analog output channels for waveform generation and analog drive functions. It can be automatically calibrated to ensure the accuracy of data collection. The PCI bus interface circuit uses PLX Technology's PCI bus interface chip PCI9030 to complete data collection and transmission of status and control signals.

System hardware circuit design

Data acquisition module design

The 8 analog input signals sent from the sensor are selected to enter the analog channel through the multi-channel analog switch ADG507. If multiple channels are collected at the same time, the time-division multiplexing method is adopted, and the on-off of each channel is sequentially controlled by the FPGA. The mode selection switch ADG509 is one of four analog switches. It can select the analog signal to be tested, the standard reference voltage value or the signal used for channel calibration after DAC conversion to enter the post-stage filtering attenuation network circuit. The signal sent to the ADC must first be low-pass filtered to filter out high-frequency noise. The filter circuit is designed as a second-order resistance-capacitance low-pass filter to filter signals with a frequency higher than 50KHz. The attenuation circuit is designed for active attenuation. The Linear amplifier's differential amplifier LTC1992 is used to complete the input signal polarity conversion and realize single-ended signal to differential signal. At the same time, the FPGA can control the relay to select different resistance networks to adjust the attenuation factor. Adjust the signal of different voltage input range to meet the input voltage range of AD7676. The signal gain programmable amplifier LTC6911 can be programmed to set a gain multiple of 1 V / V ~ 100 V / V in 1, 2, and 5 steps. During the data acquisition process, the gain amplifier gain multiple is automatically adjusted by an internal FPGA comparison circuit. Greatly improve the ability to distinguish weak signals. The AD7676 is a differential signal input. The MAX6325 reference source provides a reference voltage of 2.5V. The sampling clock is obtained from a 10MHz clock signal provided by the crystal oscillator through the FPGA internal frequency dividing circuit. The maximum single channel sampling rate is 500KSPS.

FPGA circuit design

The FPGA chip is also a special ASIC chip, which is a programmable logic device. It is developed on the basis of logic devices such as PAL and GAL. Compared with previous PAL, GAL, etc., FPGA scale is relatively large, suitable for logic circuit applications such as timing and combination. This article selects Altera's FPGA chip EP2C8Q208 to complete the timing and address decoding circuit design of the data acquisition card. Because EP2C8Q208 has 36 M4K RAMs, a 16-bit width, 4KB depth FIFO is designed inside the FPGA, and the FIFO is used to improve the data acquisition card's ability to collect and store multi-channel signals. The FIFO has half full, full, and empty flags. When the DSP detects the half full flag, the FIFO reads and writes at the same time; read only and do not write when full, and write and not read when empty. The A / D sampling control signal is controlled by the DSP through the FPGA; the DSP performs further processing on the collected data to improve accuracy. It also has the functions of a traditional CPU or MCU, and performs corresponding processing on timing, triggering, and DMA interrupt requests.

DSP circuit design

DSP uses TMS320VC5416, which is a 16-bit fixed-point DSP, with a high degree of operational flexibility and high running speed, using an improved Harvard structure (1 group of program memory buses, 3 groups of data memory buses, 4 groups of address buses) Hardware logic CPU, 128KB on-chip memory, on-chip peripherals, and a very efficient instruction set.

The role of DSP in the system is mainly to organize, mark, pack and preprocess the data after the A / D conversion data is transmitted to the host computer. All control signals of the data acquisition system are generated by the DSP control FPGA logic circuit. The DSP plug-in Flash stores the DSP program and other configuration data. At power-up, the DSP is transferred into the DSP for execution in parallel.

Calibration circuit design

The calibration circuit is an important part of this design. The high-precision performance of the data acquisition card depends not only on the high-resolution ADC, but to a greater extent depends on the excellent self-calibration and anti-noise ability of the data acquisition card.

During calibration, the DSP sends out the standard value. After D / A and A / D conversion, the collected data value is compared with the original standard value, and the deviation coefficient is taken to form a denoising equation to realize the self-calibration of the data acquisition card.

PCI bus interface circuit design

The PCI bus specification is very complex, and its interface is difficult to implement. The data acquisition card uses PCI9030 as the user interface, which provides a simple method for the development of the PCI bus interface. It is only necessary to design a simple local bus interface control circuit to realize the high-speed data transmission of the PCI bus.

System software design

Driver design

In the Windows98 / 2000 / XP environment, applications in the Windows user mode cannot directly operate the hardware device. To achieve access to the hardware resources (such as memory, interrupts, etc.) of the data acquisition card, you must write a program that runs in the core state Device driver. At present, the most used development tool is the driver development component WinDriver of GUNGO. The use of WinDriver to develop drivers does not require familiarity with the kernel knowledge of the operating system. All functions in the entire driver program work in user mode, and interact with WinDriver's .VXD and .SYS files to achieve the purpose of driving hardware. Because the WinDriver development environment provides the memory range, registers and interrupt processing modules for the PLX company chip, this article uses the GUNGO company's WinDriver5.3 development tool, which supports the PLX company's PCI interface chip, users do not need to have DDK and core mode Program development experience, can be combined with PLXmon's PLXmon tool when debugging.

Operation interface design

Use LabVIEW software of National Instruments to design the interface. LabVIEW is a graphical programming language. The operation interface simulates the control panel of the actual instrument, enabling users to complete functions such as channel selection, mode selection, gain setting, and sampling rate setting. The operation is simple and convenient.

System index analysis

ADC error analysis

Commonly used ADC mainly exists quantization error, gain error and offset error. The quantization error exists in any ADC, and can only be reduced by increasing the ADC resolution. To reduce the quantization error to ± 1LSB / 2, the usual method is to shift the transformation characteristics by 1LSB / 2. Offset error refers to the difference between the actual code and the ideal code when using a zero-volt differential input to the ADC. Gain error refers to the transition from negative full scale to

The difference between the actual slope and the ideal slope at positive full-scale input. Offset and gain errors are usually the main sources of error in ADCs. In order to perform offset calibration, this article uses a 0V or very small signal and reads the output code. If the result is positive, then the converter has a positive offset error and subtracts the offset value from the result; if the result is negative, then the converter has a negative offset error and the offset value can be added to the result. Gain calibration is achieved by applying a full-scale or near-full-scale signal to the ADC and measuring the output code. Offset calibration is performed before gain calibration.

Analog switch error analysis

Multi-way switches can be roughly divided into two types, namely analog electronic switches and mechanical contact switches. The analog switch has the advantages of fast conversion speed, long service life, small size, low cost, high integration and no jitter; but there are also some disadvantages, such as large on-resistance, inter-channel interference, and common ground between channels.

The data acquisition card designed in this paper uses ADG507 and ADG509 of ADI Company, the on-resistance Ron100 ~ 300Ω, the input signal should be divided by Ron, and the voltage output to the load resistance should be lowered. For this reason, this design uses OPA2277 to make a voltage follower connected to the back load circuit to increase the load impedance of the multi-channel analog switch and weaken the effect of the series internal resistance.

Precision design

The data acquisition card uses a programmable gain amplifier LTC6911 with a maximum adjustable gain of 100 V / V, which greatly improves the ability of the acquisition card to resolve weak signals. At the same time, the resistance attenuation network of the signal conditioning part can complete the 1/2 and 1/4 voltage division of the signal, which expands the dynamic range of the data acquisition card. Signal and interference noise are mixed together in the time domain, but have different characteristics in the frequency domain. Therefore, pre-design filters to suppress noise signals to avoid high noise levels. Receiving such signals with a gain amplifier will cause the amplifier to saturate. Make the instrument not work properly.

The voltage reference source is an important part of the A / D or D / A conversion circuit, and the system output accuracy depends largely on the accuracy of the voltage reference source. Here mainly consider the output accuracy, stability and temperature drift coefficient. The MAX6325 is a low-noise, high-precision buried Zener voltage reference chip. Its initial output voltage accuracy is as high as 0.02%, and its temperature coefficient is 0.5ppm / ° C.

Conclusion

The data acquisition card adopts 16-bit precision ADC. The design of the analog signal channel takes into account weak signal detection, noise suppression, high frequency filtering, differential amplifier circuit and programmable gain amplifier circuit. The digital circuit part is designed with EP2C8Q208 as the core, and the FPGA timing is strict , Fast speed, good programmability and other characteristics, the various control and status signals that may be needed are introduced into the FPGA, using the large capacity of FPGA and field programmable features, on-site modification according to different requirements, increasing the system design Success rate and flexibility. At the same time, DSP preprocessing the data greatly improves the accuracy of the data. In the PCB layout, careful consideration was given to filtering, grounding, and reasonable signal routing to improve the reliability of the data acquisition card.

ラベル: EP2C8Q208
 

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