Demystifying AMD's future-oriented small chip design
更新時間: 2021-10-09 11:05:46
The core idea of small chip, also translated as core grain, is to reduce the time and cost of chip development by integrating the pre-developed and designed die directly into the IC package.
The current mainstream practice is that if you want to build a high-performance chip, you need to develop a system-on-chip (SoC), and then with the advanced process of the foundry to miniaturize the functional units inside, in the same area or smaller area of the die to achieve higher performance. Obviously, as the feature size gradually approaching the physical limits, and process complexity is increasing, the more difficult this path will be more difficult to go on.
In layman's terms, the small chip approach is to build chips like building blocks. AMD, Intel, TSMC, Marvell, Cadence and other industry giants are quite concerned about it and see it as one of the options to continue Moore's Law. Here, we look at AMD's layout in terms of small chips.
It can be said that the industry's attention to small chips today, AMD has played an important role in it. Small chip concept can be traced back to the 1970s multi-chip module - the original manufactured chip and then assembled. 2014, chip design companies began to focus on this technology. 2016, the U.S. Department of Defense Advanced Research Projects Agency Darpa launched Chips project, which mentioned the chiplet Reuse idea. But the small chips really rose to fame because of the success of AMD's EYPC series of CPUs.
In 2017, AMD used small chips in its "Zen 2" architecture to develop the EYPC server processor "Naples," which, according to AMD engineers at the time, used such an innovative approach to reduce costs by According to AMD engineers at the time, this innovative approach reduced costs by half and dramatically reduced design time compared to system-on-a-chip designs. Subsequently, AMD deployed "Zen 2" small-chip technology in both consumer CPUs and enterprise EPYC processors.
AMD mentions on its website that the "Zen 2" core is a major update to the "Zen" architecture. The main advantages are as follows.
-Up to 15% increase in the number of instructions per clock cycle
-Doubling of Level 3 cache capacity (up to 32MB)
-Double the floating point throughput (256 bits)
-Double the OpCache capacity (4K)
-Infinity Fabric doubles bandwidth (512 bits)
-New TAGE branch predictor
By using small CPU cores on a 7nm process, AMD EPYC Rome processors have up to 8 chips, enabling the platform to support up to 64 cores. Small-chip technology is now widely and heavily used in AMD's EPYC server CPUs and Thread Ripper desktop CPU products.
Following the success of CPUs, AMD has plans to bring small-chip technology to the GPU space. Semiconductor manufacturing equipment also has photomask size limitations, which essentially creates a barrier to manufacturing larger GPUs, making subsequent performance improvements on a single GPU chip very difficult. In the patent AMD mentions that since most applications are built with a single GPU in mind, implementing small chip designs on GPUs has always been a major challenge in order to preserve the existing application programming model.
To address this challenge, AMD uses a high-bandwidth interconnect to facilitate communication between the small chips, a cross-connection AMD calls HBX. The method is implemented specifically by connecting the CPU to the first GPU small chip and using a passive interconnect to connect the L3 cache to the rest of the channel between the small chips. This means that in the case of the CPU, it communicates with a large GPU instead of a bunch of small GPUs. From a developer's perspective, the GPU model does not change.
At COMPUTEX 2021, Lisa Su, President and CEO of AMD, shared AMD's latest progress on 3D small chips. She said AMD continues to build on its leading IP and investment in leading manufacturing and packaging technologies with AMD 3D small-chip technology, a packaging breakthrough that combines AMD's innovative small-chip architecture with 3D stacking using an industry-leading hybrid bonding approach to deliver more than 200 times the interconnect density, with more than 15 times the number and density of 2D small chips than existing 3D packaging solutions . The industry-leading technology, pioneered in close collaboration with TSMC, also consumes less energy than current 3D solutions and is the world's most flexible active-to-active silicon stacking technology.