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FPGA, STRATIX II, 30K ELEMENTS, FBGA672
| メーカー : | Intel Corp |
|---|---|
| パッケージ : | FBGA-672 |
| 製品 : | FPGA - Field Programmable Gate Array |
| Datasheet: | EP2S30F672C5N Datasheet (PDF) |
| RoHs Status: | Rohs |
| 在庫: | 2000 |
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EP2S30F672C5N 製品詳細
Introduction
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions. Various high-speed external memory interfaces are supported, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM. Stratix II devices support various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry. Stratix II devices offer a complete clock management solution with internal clock frequency of up to 550 MHz and up to 12 phase-locked loops (PLLs). Stratix II devices are also the industry’s first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm to protect design.
Features
The Stratix II family offers the following features:
■ 15,600 to 179,400 equivalent LEs; see Table 1–1
■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
■ TriMatrixmemory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
■ Support for numerous single-ended and differential I/O standards
■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance
■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
■ Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
■ Support for design security using configuration bitstream encryption
■ Support for remote configuration updates
アプリケーション/パラメータの範囲
The Stratix II family offers the following features:
■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
■ TriMatrixmemory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
(商品画像: Diagram)
技術的パラメータ
- Series
- Stratix II
- Number of Logic Blocks
- 1694
- Number of I/Os
- 500
- Operating Supply Voltage
- 1.2 V to 3.3 V
- Maximum Operating Temperature
- + 70 C
- Mounting Style
- SMD/SMT
- Package / Case
- FBGA-672
- Distributed RAM
- 1.4 Mbit
- Minimum Operating Temperature
- 0 C
- Operating Supply Current
- 0.3 A
- Packaging
- Tray
EP2S30F672C5N Datasheet
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EP2S30 Family PDF Datasheet
EP2S30F672C5N 特殊な製品に関連する
Ratings and Reviews (3)
- 5 / 5
- 5 Stars 100%
- 4 Stars 0%
- 3 Stars 0%
- 2 Stars 0%
- 1 Stars 0%
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**orri***2020-03-28
Excellent transaction!! Thanks
-
**s. B***2017-11-14
Many thanks, super service, price and product.
-
**оман***2017-10-20
еще не ставил.новое.Спасибо ..
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保証
1.The electronic components you purchase include 365 Days Warranty, We guarantee product quality.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
FAQ:
- Q: How does Jotrin guarantee that EP2S30F672C5N is the original manufacturer or agent of INTEL?
- We have a professional business development department to strictly test and verify the qualifications of INTEL original manufacturers and agents. All INTEL suppliers must pass the qualification review before they can publish their EP2S30F672C5N devices; we pay more attention to the channels and quality of EP2S30F672C5N products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
- Q: How to find the detailed information of EP2S30F672C5N chips? Including INTEL original factory information, FPGA - Field Programmable Gate Array application, EP2S30F672C5N pictures?
- You can use Jotrin's intelligent search engine, or filter by Stratix II FPGA category, or find it through Intel Corp Information page.
- Q: Are the INTEL's EP2S30F672C5N price and stock displayed on the platform accurate?
- The INTEL's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for EP2S30F672C5N, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Note: It may take up to 24 hours before carriers will display tracking information. In normal conditions, Express delivery needs 3-5 days, Registered Mail needs 25-60 days. - Q: What is the process for returns or replacement of EP2S30F672C5N?
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All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the EP2S30F672C5N we delivered, we will accept the replacement or return of the EP2S30F672C5N only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of EP2S30F672C5N.
(3)The EP2S30F672C5N is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy. - Q: How to contact us and get support, such as EP2S30F672C5N datasheet pdf, EP2S30 pin diagram?
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